ISCA

ACM/IEEE ISCA paper using IEEE conference style. Two-column, performance/power/area results.

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Conference

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Free to use (MIT)

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isca/main.tex

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\documentclass[conference,letterpaper]{IEEEtran}
\IEEEoverridecommandlockouts
\usepackage{cite}
\usepackage{amsmath,amssymb}
\usepackage{graphicx}
\usepackage{booktabs}
\usepackage{hyperref}

\begin{document}

\title{Chronos Cache: Speculation-Safe Data Prefetching\\
       for Shared Last-Level Caches}

\author{\IEEEauthorblockN{First Last, Jane Doe, John Smith}
\IEEEauthorblockA{\textit{University of Example}\\
\{you, jane, john\}@example.com}}
\maketitle

\begin{abstract}
Cache prefetching is a major performance contributor but creates
significant microarchitectural side-channel risk. Chronos Cache
preserves most of the performance of aggressive prefetching while
provably blocking a broad class of timing-based attacks on the shared
LLC. On SPEC CPU 2017, Chronos delivers 89\% of baseline prefetcher
speedup at 2\% area overhead.
\end{abstract}

\begin{IEEEkeywords}
cache prefetching, side channels, microarchitecture
\end{IEEEkeywords}

\section{Introduction}
Prefetchers speculate; speculation leaks. We show how to recover most
of the performance benefit with provably bounded leakage.

\section{Threat Model}
Cross-core attacker sharing LLC with a victim, measuring cache-line
access latencies.

\section{Chronos Design}
Three mechanisms: (i) per-partition prefetch buffers; (ii) randomized
eviction at the boundary; (iii) rate-limited inter-partition prefetch
coordination.

\section{Security Analysis}
We prove that the prefetcher leaks at most $O(\log n)$ bits per epoch
under Prime+Probe attack.

\section{Evaluation}
\begin{table}[t]
\centering\small
\begin{tabular}{lccc}
\toprule
Benchmark & Baseline & Secure (Prior) & \textbf{Chronos} \\
\midrule
SPEC-INT geomean & 1.18 & 1.04 & \textbf{1.16} \\
SPEC-FP  geomean & 1.24 & 1.07 & \textbf{1.21} \\
\bottomrule
\end{tabular}
\caption{Performance relative to a no-prefetch baseline.}
\end{table}

\section{Conclusion}
Security-conscious prefetcher design need not sacrifice most of the
performance benefit of speculation.

\bibliographystyle{IEEEtran}
\bibliography{refs}
\end{document}
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