LaTeXProjectReportCSE460

%! Author = ιηмσяєѕєηтυм
%! Date = 4/2/23

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\begin{document}

    \title{Design a 4-bit ALU\\
    {\footnotesize Group: \textit{4 CSE460 Lab Section 9}}
    }

    \author{\IEEEauthorblockN{ATHAR NOOR MOHAMMAD RAFEE}
    \IEEEauthorblockA{\textit{DEPT: CSE} \\
    \textit{ID: 20101396} \\
    Section: 9L \\
    noor.mohammad.rafee@g.bracu.ac.bd}
    \and

    \IEEEauthorblockN{A.S.M MAHABUB SIDDIQUI}
    \IEEEauthorblockA{\textit{DEPT: CSE} \\
    \textit{ID: 20301040} \\
    Section: 9L \\
    asm.mahabub.siddiqui@g.bracu.ac.bd}
    \and

    \IEEEauthorblockN{Ayon Das}
    \IEEEauthorblockA{\textit{DEPT: CSE} \\
    \textit{ID: 20301099} \\
    Section: 9L \\
    ayon.das@g.bracu.ac.bd}
    \and

    \IEEEauthorblockN{MD. SAKIB}
    \IEEEauthorblockA{\textit{DEPT: CSE} \\
    \textit{ID: 20301180} \\
    Section: 9L \\
    md.sakib1@g.bracu.ac.bd}
    \and

    \IEEEauthorblockN{ MOHAMMED INZAM UL AZAM}
    \IEEEauthorblockA{\textit{DEPT: CSE} \\
    \textit{ID:20101144} \\
    Section: 09L \\
    mohammed.inzam.ul.azam@g.bracu.ac.bd}
    }

    \maketitle

    \begin{abstract}
        This project presents the design and implementation of a 4-bit Arithmetic Logic Unit (ALU).
        The ALU performs arithmetic and logical operations on two 4-bit inputs and produces a 4-bit output.
        The design is implemented using Verilog hardware description language and simulated using timing function.
        The ALU supports basic arithmetic operations such as \textit{ADD} and \textit{SUB},
        as well as logical operations such as NAND, and XNOR
        as per requirements of the project.
        Overall, this project demonstrates the design and implementation of a simple but
        functional sequential ALU using Verilog HDL.
    \end{abstract}

    \begin{IEEEkeywords}
        ALU, Verilog HDL,  opcode, timing diagram, SUB, XNOR, NAND, ADD, RESET
    \end{IEEEkeywords}


    \section{Introduction}\label{sec:introduction}
    \input{sections/introduction}


    \section{Finite State Machine Design and Implementation}\label{sec:FSM}
    \input{sections/finite-state-machine-design-and-implementation}


    \section{Verification}\label{sec:verification}
    \input{sections/verification}


    \section{Conclusion}\label{sec:conclusion}
    \input{sections/conclusion}

    \appendix


    \section{Appendix}\label{sec:appendix}
    \input{sections/appendix}

\end{document}